Process for depositing metal contacts on a buried grid solar cell and solar cell obtained by the process

ABSTRACT

A buried grid solar cell is manufactured by a process for metallising one or more metal contacts of a buried grid solar cell having a body of doped semiconductor material, wherein the electrical contact(s) is/are provided by conducting material being arranged in a pattern of one or more grooves into the semiconductor material by an electrolytic metal deposition process comprising a conventional electrolytic bath containing a special combination of per se known additives.

TECHNICAL FIELD

[0001] The present invention relates to a process for the metallising,i.e. deposition of metal, of one or more contacts of a buried grid solarcell having a body of doped semiconductor material, which body has twomajor opposing surfaces forming a light incident surface and a backsideboth provided with one or more electrical contacts, and which bodyfurther has one or more edges between the major opposing surfaces,wherein the electrical contact or contacts at the light incident surfaceis/are formed by conducting material being arranged in a pattern of oneor more grooves into the semiconductor material at the light incidentsurface. Furthermore the invention relates to a buried grid solar cellmanufactured by such a process.

BACKGROUND ART

[0002] The cost of photovoltaic (PV) solar cell production forterrestrial applications has declined 7-fold since 1980 through,innovation in manufacturing processes and improvements in productperformance. However, further reductions in manufacturing costs arenecessary before we can expect widespread use of PV solar cells in therenewable energy market. Accordingly, there is still a need for furthercost savings in the manufacture of solar cells by improved processtechnology.

[0003] A common feature of all solar cells is the requirement of metalcontacts to be applied to both the positive and negative surface of thedevice to carry the photo-generated current. The contacts must berobust, highly conducting, of low-cost and above all, simple andefficient to fabricate. Copper plated contacts are used in thefabrication of PV solar cells. The high electrical conductivity ofcopper is ideal for this application but the current deposition processby electroless plating is somewhat slow and inefficient. Furthermore thecost and handling of large amounts of chemicals is an increasing problemconnected with electroless copper plating.

[0004] PV solar cells are generally based on the use of a dopedsemiconductor material. In one type of solar cells silicon is used asthe semiconductor. This kind of solar cell typically comprises apre-manufactured p-type doped silicon wafer. For the preparation of asolar cell this wafer is doped from the light incident surface to formn-type silicon at the surface. In this way a gradient interface betweenn-type and p-type silicon, termed a p-n-junction, is established. Thep-n-junction produces the electrical field which makes the chargecarriers move in one direction. To be able to conduct the electricalcurrent away from the cell, metal contacts are provided on the cell.These contacts act as the positive and negative contact to the cell.However, by arranging metal contacts on the light incident surface thesecontacts reduce the active area on the light incident surface of thesolar cell and thus reduce the efficiency of the cell. Accordingly it isimportant to minimize the shading effect of these metal contacts.

[0005] In U.S. Pat. Nos. 4,726,850 and 4,748,130 and the correspondingAU patent No. 570 309 (Green and Wenham) from 1984 a buried grid solarcell is disclosed in which the metal contacts on the light incidentsurface are embedded in grooves in the surface to reduce the shadingeffect and to improve the electrical contact with the semiconductor. Inthe patent specifications a number of methods for providing the metalcontacts are listed. These include: sweeping of silver paste into thegrooves, solder dipping and electroplating. However, the electroplatingprocess is not exemplified in the patent specifications.

[0006] Use of a conventional electroplating process for the preparationof an embedded contact material in the type of grooves used in the aboveknown buried grid solar cell would lead to an undesired formation ofvoids in the internal space of the grooves when the metal contactmaterial is built up on exposed surfaces. Such voids will reduce theeffectively as an electrical conductor. Furthermore the contact materialwill also build up on the electrically insulating light transparentlayer in the areas adjacent to the grooves shadowing for the incidentlight to the solar cell and reducing its efficiency. Thus, although useof electroplating for the preparation of the embedded contacts wasmentioned by Green and Wenham in 1984 this approach has not been furtherdeveloped before the present invention.

[0007] In the electroplating industry it is common practice to usespecific additives in the electroplating baths. Among such per se wellknown additives used in electrolytic copper plating are levellingadditives. Levelling additives ensure a laminate growth during the buildup of the electroplated layer and they are effective to level minorscratches in the basic material being electroplated. Such scratches arenormally in the order of 0.1 to 5 μm width and 0.1 to 5 μm depth.

[0008] Another type of well known additives used in electrolytic copperplating are suppressing additives acting as diffusion controlled platinginhibitors. Such suppressing additives inhibit the build up of metal inareas having higher field intensity, such as at elevated areas beingclosest to the anode.

[0009] In Plating & Surface Finishing, March 2000, pp. 81-85, Mikkola etal. disclose a copper electroplating process using brighteners,levellers and suppressing agents for void-free gap fill of trenches ofsub-micron dimensions used for interconnects in the area ofsemiconductor devices. In this article it is stressed that control ofcurrent density and additive levels has a dramatic effect on the gapfill mechanism. However, no detailed information concerning the specificcomposition of the electrolytic baths is given, and no information isgiven in case of bigger grooves such as grooves being about 20-50 μm indepth and 10-30 μm in width.

[0010] Thus, prior to the present invention a process for providingelectrical contacts having good electrical conductivity and noadditional shading beyond that defined by the groove dimension (width)on a buried grid solar cell, was needed.

[0011] It has now been found that it is possible to completely fill thegrooves in a solar cell of the type in which grooves typically have adepth of 20-50 μm and a width of 10-30 μm using a simple electroplatingtechnique involving a conventional electroplating bath with a specialcombination of per se known additives obtaining effective embeddedconducts without voids and no overplating on the light incident surfaceoutside the grooves.

BRIEF DESCRIPTION OF THE INVENTION

[0012] Accordingly the present invention relates to a process for themetallising of one or more contacts of a buried grid solar cell having abody of doped semiconductor material, which body has two major opposingsurfaces forming a light incident surface and a backside both providedwith one or more electrical contacts, and which body further has one ormore edges between the major opposing surfaces, wherein the electricalcontact or contacts at the light incident surface is/are formed byconducting material being arranged in a pattern of one or more groovesinto the semiconductor material at the light incident surface,comprising the steps of

[0013] a) providing the semiconductor body with a p/n-junction and anelectrically insulating layer on the light incident surface andoptionally on other surfaces, which layer is light transparent and notcatalytic for electroless plating,

[0014] b) providing an exposed surface on one or more of the edges,

[0015] c) providing one or more grooves with a depth of 20-50 μm fromthe light incident surface through the insulating layer and into thesemiconductor body and a width of 10-30 μm at the level of the lightincident surface,

[0016] d) doping the exposed material in the grooves obtained in step c)to reestablish the p-n-junction in the material below the surface in thegrooves,

[0017] e) applying a seed layer on the exposed semiconductor material inthe grooves by electroless plating followed by sintering,

[0018] f) applying an electrically conducting base layer by electrolessplating on top of the seed layer obtained in step d), and

[0019] g) filling the grooves with an electrically conducting contactforming material by electrolytic plating using a conventionalelectrolytic bath further comprising a levelling additive and asuppressing additive and using substantially constant cell voltage.

[0020] Furthermore the present invention relates to a buried grid solarcell comprising a body of doped semiconductor material having two majoropposing surfaces forming a light incident surface and a backside bothprovided with one or more electrical contacts and which body further hasone or more edges between the major opposing surfaces, wherein theelectrical contact or contacts at the light incident surface is/areformed by conducting material being arranged in a pattern of one or moregrooves into the semiconductor material at the light incident surface,which light incident surface is provided with an electrically insulatinglight transparent coating layer interrupted by the grooves, whichgrooves have a depth of 20-50 μm and a width of 10-30 μm at the level ofthe light incident surface, and have a seed layer coating the surfacesin the grooves on the top of which the grooves have an electricallyconducting base layer, on the top of which the grooves again are filledwith a electrically conducting contact forming material essentiallywithout voids and no overplating on the electrically insulating lighttransparent layer.

[0021] A key feature of the process according to the present inventionis the use of a levelling additive and a suppressing additive combinedwith constant cell voltage.

[0022] A further key feature according to a preferred embodiment of theinvention is the method for obtaining an effective electrical contactfor the electrolytic plating step by the combination of a seed layer anda following electrically conducting base layer by electroless platingboth in the grooves and on at least one edge portion forming a contactto the jig of the used electrolytic plating device.

[0023] Thus, in the electroplating step according to the presentinvention, wherein the contact forming material is deposited, the buildup of contact forming material is—due to the levelling additive and thesuppressing additive—proceeding from the bottom of the groove, and thebuild up of contact forming material proceeds in such a way, thatessentially layer upon layer of this material is deposited. Thedeposition essentially stops when the grooves are full.

[0024] By the prior art method of Green and Wenham mentioned above forthe electroless copper plating for providing metal contacts in groovesat the light incident surface of a solar cell, the copper ions in thecopper solution bath used are reduced to free metal by use of a chemicalreducing agent. Typically formaldehyde or—when used as an aqueoussolution—formalin is employed and the use of this compound requiresspecial precautions for safe handling and disposal due to the healthrisks presented by this compound. In the method of the present inventionthe reduction of the copper ions to elemental copper is provided byelectrons from an outside power supply and no chemical reducing agent ispresent and thus no such health risks exist by using the method of thepresent invention.

[0025] In general the method of the present invention is moreenvironmentally safe compared to the electroless plating technique ofprior art. As an example it can be mentioned that in the process ofprior art about 30% of the copper in solution has to be discarded asonly about 70% of the copper in the solution is deposited on the waferwhereas almost 100% of the copper in the solution employed in theprocess of the present invention is deposited on the wafer. The reasonfor the mere 70% utilisation of the copper in the prior art technique isthat the copper solution has to be refreshed quite frequently.Furthermore it is very difficult to remove the copper ions from thediscarded solution because of complex builders which very effectivelykeep the copper ions in solution. Accordingly this adds furtherenvironmental problems to the method of prior art.

[0026] Another advantage of the process of the present invention is thatthe plating rate is up to 30 times faster compared with the electrolesstechnique of prior art. That is, a sufficient amount of copper metaldeposition in the grooves and at other desirable locations on the wafercan be accomplished in only 3 minutes. As a result of this shortprocessing time and due to the fact that the concentration of the copperions in the bath are held nearly constant because the amount ofdeposited copper is compensated by an equal amount of copper dissolvedfrom copper anodes this step of the method of the present invention issuitable for a continuous conveyor process.

[0027] Yet another advantage of the process of the present inventionover prior art is that the chemicals used for electrolytic copperdeposition in general are significantly cheaper than the chemicals usedfor electroless copper deposition.

[0028] Finally, prior to the electroless plating technique according toprior art, if scratches appear in the light incident surface through thedielectric layer, these scratches will automatically be plated withcopper during said electroless plating process resulting in a slightlyshading effect as well as an undesirable appearance. This problem doesnot exist for a semiconductor body that is to be plated with anelectroplating process according to the present invention since theelectroplating process is not an autocatalytic process as theelectroless plating. Thus electrolytic plating will only take place onareas being in electrical contact with the cathode (minus pole) of therectifier.

[0029] A rough estimate suggests that considerable cost savings isobtainable by the process of the present invention compared to theprocess of prior art. With an anticipated world wide increase inproduction of buried grid solar cells of a factor of four to five overthe next five years, the advantages listed above will surely becomequite beneficial in terms of economy as well as environmental concerns.

[0030] The extent of applicability of the invention appears from thefollowing detailed description. It should, however, be understood thatthe detailed description with drawings and specific examples is merelyincluded to illustrate the preferred embodiments, and that variousalterations and modifications within the scope of protection will beobvious to persons skilled in the art on the basis of the detaileddescription.

DRAWINGS

[0031]FIG. 1a is a SEM image of a groove filled by electrolytic copperplating according to the invention,

[0032]FIG. 1b is a SEM image of a groove only half filled byelectrolytic copper plating according to the invention, and

[0033]FIG. 2 is a SEM image of a groove filled by electroless copperplating according to the prior art.

DETAILED DESCRIPTION OF THE INVENTION

[0034] The present invention relates to an improvement of photovoltaicburied grid solar cells of the type based on a body, such as a wafer, ofdoped semiconductor material and provided with embedded contacts on thefront surface. The invention also relates to an improvement of theprocess for the preparation of such solar cells.

[0035] According to a preferred embodiment the solar cells are made withdoped silicon as the active semiconductor device. Usually this is in theform of a silicon wafer typically with a square form of up to 150×150 mmor a round form up to 150 mm in diameter and with a thickness of about250-400 μm. The silicon can be a single crystal (known asmonocrystalline) or can contain many small crystals (referred to amulticrystalline or polycrystalline).

[0036] The silicon wafers used usually comprise a p-type silicon wafer.The light incident surface of the wafer is doped by use of a phosphoruscompound, such as POCl₃, at 800-900° C. to make it n-type and producethe basic p/n-junction which is the active component of the solar cell.

[0037] To enable the photogenerated free electrons to be carried awayfrom the solar cell metal contacts are applied to the light incidentfront surface (the n-type surface) and to the backside surface (thep-type surface). On the front surface it is important that the contactcovers a minimum of the area of this surface to enable light to passthrough into the silicon.

[0038] This is ensured in the so called buried grid solar cell by anelectrically conducting material embedded in grooves, which are cut in agrid pattern into the front surface of the solar cell wafer as disclosedin the U.S. Pat. Nos. 4,726,850 and 4,748,130. The embedded conductingmaterial in the grooves forms a pattern of electrically conducting gridline members.

[0039] The grid line members should be as narrow as possible in order tominimize the portion of the light incident surface, which will be shadedby the grid line members. The smaller ratio of shaded light incidentsurface the higher is the cell performance. Cell performance is usuallymeasured in terms of efficiency at standard test conditions—electricalenergy out divided by total incident sunlight energy.

[0040] Before the grooves are cut into the front surface this surface isprovided with a top surface coating of an electrically insulating layer,which layer is light transparent and not catalytic for electrolessplating. The coating acts as an anti-reflection layer. In connectionwith the present invention the electrically insulating layer is offurther importance because such a dielectric (non-conducting) layer willprevent metal plating on unwanted regions of the light incident frontsurface. In the preferred embodiment the electrically insulating layeris a silicon nitride coating on the silicon surface. An alternativeelectrically insulating layer may be of silicon dioxide.

[0041] The grooves are cut into the front surface of the wafer using alaser in the presently preferred embodiment. Alternatively the groovescan be mechanically formed using a diamond saw. Further alternativescomprises chemically etched grooves or plasma etched grooves.

[0042] The grooves have a depth of 20-50 μm from the light incidentsurface and thus penetrate through the insulating silicon nitride layerand into the semiconductor body. The width is 10-30 μm at the level ofthe light incident surface. In this way the p-type silicon can beexposed in the grooves and in that case it will be necessary to dope thesurfaces inside the grooves to obtain n-type silicon and thusreestablish the p-n-junction.

[0043] An essential feature of the present invention is the way, inwhich the metal contacts are established, especially the grid linemembers embedded in grooves on the front surface, but in a furtherpreferred embodiment also the contact on the backside. Thisestablishment of electrically conducting metal contacts is also termedmetallisation.

[0044] In a commercial buried grid solar cell manufactured in accordancewith the above mentioned U.S. Pat. Nos. 4,726,850 and 4,748,130 the gridline members are prepared by the deposition of a thin (typically 0.1 μm)nickel seed layer by electroless nickel plating, sintering of the nickellayer to the silicon surface at a temperature of typically 400° C. in aninert atmosphere (nitrogen, argon or forming gas) to produce an ohmiccontact to the silicon with high mechanical adhesion. On the top of thisthin seed layer of nickel a nickel base layer of about 0.1 μm isdeposited by electroless plating. Thereafter the main electricallyconducting part of the grid line members is provided by the depositionof the main copper conductor (typically 5 μm) by electroless copperplating. A SEM image of an electroless copper plated groove preparedaccording to this commercial method is shown on FIG. 2. It appears fromFIG. 2 that also the surface adjacent to the groove is overplatedwhereby a part of the light incident surface is shadowed. Furthermorethe groove is not filled with the contact forming copper as the centralpart of the cross section is void. Such void part reduces the electricalconductivity of the grid line member.

[0045] Furthermore voids which have been formed during a plating processmay present a hidden problem which is difficult or impossible to detectin the testing procedure following the manufacturing steps. Corrosiveplating solution may be captured or enveloped in the voids and may bedifficult or impossible to remove by rinsing. Such plating solution mayleak later on and it may discolour and even destroy the solar cell bycorroding the contacts, solderings etc.

[0046] According to the present invention the metallisation isestablished by first applying a thin seed layer of electroless nickelfollowed by sintering in the same way as by the commercial process. Thena relatively thick base layer of about 2 μm nickel is deposited by anelectroless deposition process on the top of the seed layer. This baselayer acts as a conductor for the copper plating to follow and mayalso—depending on the thickness—function as a barrier to diffusion ofcopper into the silicon. Finally the grooves are filled by electrolyticcopper plating. As it appears from FIG. 1a it is now possible to fillthe grooves without voids and without overplating of the light incidentsurface.

[0047] The two electroless plating steps differs from each other. Thusthe purpose of the seed layer is to create a contact to the silicon aswell as a seed catalysing the following plating. The term “seed layer”is not to be understood as a continuous layer covering the exposedsilicon surface. Thus it will often be merely arrays of clusters ofmetal “grains” distributed on the exposed silicon surface. Each clusterwill be a catalytic seed for the following electroless plating of a baselayer, the latter being a real continuous layer. A suitable system forthe preparation of a nickel seed layer is the AL100 bath fromEnthone™-OMI.

[0048] The base layer has to be a layer with high conductivity whichacts both as the cathode in the following electrolytic copper platingstep and as a contact member between the silicon and the contact formingmaterial in the final solar cell. This is ensured by using a low contentof phosphorus in the final electroless deposit. Furthermore the baselayer should have low internal mechanical stress. It would be desirableif the base layer bath is stable and easy to handle and operate. Asuitable low phosphorus, low temperature, high speed, electrolessprocess for the preparation of a nickel base layer is Enplate™ Ni 429 Ebath from Enthone™-OMI.

[0049] The first application of a thin seed layer of electroless nickelis common to the known commercial process and the process according tothe invention. This step requires a surface, which is catalytic forelectroless plating. Such catalytic surfaces are the exposed siliconsurfaces in the grooves, whereas the silicon nitride layer on the lightincident surface is not catalytic for electroless plating. In order toensure a good contact to the clamping jig of the electrolytic platingdevice used in the electrolytic copper plating step an exposed siliconsurface is provided on at least one of the edges of the silicon waferadjacent to at least one end of the grooves before the seed layer isapplied. In this way the seed layer is not only applied in the exposedsurfaces in the grooves, but also on said edge or edges. In this way thebase layer on the top of the seed layer will be an electricallyconductive integrated layer covering both the groove surfaces and theedge or edges in a communicating way.

[0050] In the normal cell processing sequence, silicon nitride may alsobe coated around the edge of the wafer. If left in place thiselectrically insulating silicon nitride would result in poor electricalcontact to the wafer. Accordingly, to expose the silicon surface thesilicon nitride is removed from the edge of the wafer, for example byplasma-etching in a C₂F₆-oxygen plasma. The wafers are “coin-stacked”such that only the edges of the wafers are exposed to the plasma. Othertechniques could be considered for removing the silicon nitride,including abrasion or a high-velocity waterjet method.

[0051] As described above the exposed Si-edges are plated with first aseed layer and then a thicker base layer of electroless plated nickel.In the following step these nickel-plated edges of the wafer will make agood electrical contact to the plating jig during the electrolyticcopper plating process.

[0052] After the electroless nickel plating the grooves are filled inthe electrolytic copper plating process using a conventionalelectrolytic bath based on copper sulphate (CuSO₄.5H₂O) and sulphuricacid (H₂SO₄) and further comprising a levelling additive and asuppressing additive and using substantially constant cell voltage.

[0053] Levelling additives (levellers) which have been found to beuseful in the process of the present invention include compoundscontaining thiocarbamide group(s) (—C(S)—NH—) or its correspondingtautomeric mercapto form. Examples of these compounds are thiourea andits derivatives, such as 1-ethylthiourea, 1,3-diethylthiourea,1-phenylthiourea etc. (see for example U.S. Pat. No. 3,682,788),2-imidazolidine-thione, 2-thiazolidinethione, 2-pyrimidinethiol etc.(see for example U.S. Pat. No. 3,542,655).

[0054] Another type of compounds useful as levelling additives in theprocess of the present invention are cations with a relatively highmolecular weight, such as phenazonium dyestuffs, e.g. compounds knownas: Janus Green, Janus Black, Neptune Blue etc. Also polymericphenazonium compounds have shown to possess very potent levellingproperties. Examples of these includepoly(6-methyl-7-dimethylamino-5-phenyl-phenazonium sulphate),poly(2-methyl-7-dimethylamino-5-phenyl-phenazonium sulphate),poly(2,5,8-triphenyl-7-dimethylamino-5-phenyl-phenazonium sulphate).Also certain cationic polymers, such as polyalkylene imines, polymersand copolymers of 2-vinylpyridine and/or 2-methyl-5-vinylpyridine areuseful levelling additives in the process of the present invention.

[0055] Derivatives of dithiocarbamic acid, such asN,N-diallyl-dithiocarbamic acid-n-propylester-ω-sodium sulphonate andN-alkyl-dithiocarbamic acid-n-propylester-ω-sodium sulphonate, whereinthe alkyl group typically contains 1-5 carbon atoms (see e.g. U.S. Pat.No. 3,798,138) are also useful as levelling additives according to theprocess of the present invention.

[0056] The concentration of the above mentioned compounds in the processof the present invention typically range from 0.001 g/l to 0.05 g/l.However, the dithiocarbamic acids may be used at considerably higherconcentrations. The most potent levellers of the above compounds are thephenazonium compounds.

[0057] To prevent overplating at the areas closer to the anode (e.g. atthe top edges of the grooves) suppressing additives (suppressors) arefurther included in the electrolytic bath used in the process of thepresent invention. It has been found that organic disulphides of thetype R₁—S—S—R₂, wherein R₁ and R₂ may be the same or different and arealkyl sulphonate groups, are very useful as suppressing additives. Anexample of a suppressing additive useful in the process of the presentinvention is bis(sodiumpropylsulfonic acid)disulfide. Typicallyconcentrations of the suppressing additive range from 10-20 mg/l.

[0058] Optionally a carrier brightener may be included in the bathcomposition of the process of the present invention. The properties of acarrier brightener is to improve the performance of the other additivesas well as brightness by providing uniform, small-grained, brightdeposits. A group of oxygen containing high molecular weight compounds(molecular weight of 1000 to 20,000) has shown to provide excellentbrightening properties. This group include polyvinyl alcohol,polyethylene glycol, polypropylene glycol, alkylphenolpolyglycolethers(the alkyl group typically being octyl, nonyl or dodecyl),polyethylene-polypropyleneglycol block polymers, and finally copolymersof ethylene oxide and propylene oxide. When included the concentrationof these specific carrier brighteners amount from 0.001 to 1 g/l.

[0059] Due to the fact that the surface adjacent to the grooves has anelectrically insulating layer of silicon nitride and by use of theadditives it is possible to fill the grooves without voids andoverplating with the electrolytic copper plating technique.Conventionally electrolytic processes are carried out at a givenselected current density. By the present invention use is made of aconstant cell voltage, such as 0.5-5 V or more, preferably 0.8-3 V, andmore preferred 1-2 V, which means that the initial current density islow and rises rapidly as the deposits grow.

[0060] In a preferred embodiment the grooves provided in the waferincludes (i) a first group consisting of a number of essentiallyparallel grooves distributed mutually spaced over the major part of thelight incident surface, and (ii) a second group of one or more bundlesof narrowly spaced grooves intersecting the first group of grooves (i).In this case the metallisation steps provide a corresponding first groupof embedded conductors and a corresponding second group of embeddedconductors, which second group of conductors forms one or more bundlebus-bars electrically connected at the points of intersection to thefirst group of embedded conductors. Such pattern of the embeddedconductors or grid line members is advantageous for the conducting andhence utilisation of the electrical current generated in the solar cell.

[0061] Preferably the exposed surface of semiconductor material in oneor more of the grooves in at least one end is extended to at least apart of at least one adjacent exposed edge surface prior to themetallisation. In this way the seed layer and the electricallyconducting base layer provided in steps (e) and (f), respectively, willbe applied not only on the exposed surfaces in the grooves, but also onthe thus communicating exposed surfaces on the edge. This ensures anelectrical contact between the base layer formed in the grooves and abase layer formed on said part(s) of the edge(s) which again ensures agood electrical contact from a clamping jig of an electrolytic platingdevice used in the electrolytic copper plating step (g) through the baselayers on the edges to the base layers in the grooves.

[0062] As already mentioned above a solar cell is also provided with acontact on the back surface. In the above described commercial buriedgrid solar cell prepared according to Wenham and Green (U.S. Pat. Nos.4,748,103 and 4,726,850) this back surface contact is provided by thedeposition of aluminium on the back surface of the wafer by evaporationfollowed by sintering prior to the metallisation steps. In this way theelectroless nickel and copper plating will also cover the aluminiumdeposit on the back surface as the final backside contact. A picklingstep for the activation of the sintered aluminium coating on thebackside may optionally be performed prior to the plating process iffull metal coverage is desirable. This activation can be made by aspecial pretreatment comprising etching of the sintered aluminium oxidein a mixture of HF and H₂SO₄.

[0063] In a preferred embodiment of the present invention the inventiveprinciple of metallisation is also used on the backside. Thus theinventive process can be carried out using a semiconductor body whichhas been provided with a coating of aluminium on the backside in a steppreceding the application of the seed layer in step e). In this case thealuminium coating is optionally activated and the steps (e+f+g) furtherinclude application of a seed layer, a base layer and a deposit of thecontact material, respectively, on the aluminium coating. In this waythe electrically conducting base layers on the grooves and edge(s) andthe backside are formed as an integrated electrically communicating unitin step (f) and in step (g) the contact forming material is deposited asan integrated electrically communicating deposit in the grooves, on theedge(s) and on the backside. After the metallisation steps a portion ofthe electrically conducting layers on the edge(s) formed in steps(e+f+g) has to be removed to eliminate a short-circuit through theelectrically conducting layers on the edge(s) between the electricalcontacts on the two major opposing surfaces of the semiconductor.

[0064] A preferred method for this removal of the metal (nickel andcopper layers) at the edges of the solar cell after plating to avoid anelectrical short-circuit is to laser-scribe a groove in the frontsurface or in the back surface at a small distance from the edge of thewafer, typically 1 mm, and approximately one third into the thickness ofthe wafer. The metallised edges of the cell are then removed bysnapping-off (cleaving) the edge strips. Other methods of removing themetal from the edge might be considered, including mechanical abrasionand reactive plasma-etching.

[0065] In the above mentioned embodiment having two groups of groovesincluding (i) a first group consisting of a number of essentiallyparallel grooves distributed mutually spaced over the major part of thelight incident surface, and (ii) a second group of one or more bundlesof narrowly spaced grooves intersecting the first group of grooves (i),and wherein the corresponding second group of conductors forms one ormore bundle bus-bars electrically connected to the first group ofembedded conductors, the electrolytic plating step may be carried outunder such conditions, that the jig is clamped to an electricallyconducting layer on one of the edges communicating with the second groupof one or more grooves and that the semiconductor body is lifted from orlowered into the electrolytic bath during the plating step (g) in such away that grooves of the first group located at further distance from theelectrically conducting layer on said edge are submerged for a longerperiod of time in the bath as compared to grooves of the first groupcloser to said edge. This ensures the desired uniform deposit in thegrooves because the groove surface parts having a long distance to thejig will be immersed for a longer period of time than those parts beingcloser to the jig where the deposition would be higher in case of thesame time of immersion.

[0066] The body of semiconductor material is preferably made of dopedsilicon. However, any semiconductor material can be used in theinventive solar cell. Examples of other semiconductor materials aregallium arsenide, indium phosphide, copper indium selenide and zincoxide.

[0067] The seed layer acts as a seed for the following metallisationsteps. Preferred seed layers are made of nickel or alloys thereof.Examples of other possible metals for the seed layer comprise Pd, Au,Ag, Co and Sn and alloys thereof.

[0068] The base layer may act as an inert barrier for migration bydiffusion of copper into the semiconductor material because suchmigration is a “life-time killer” of the solar cell. Furthermore itshould be sufficiently electrically conducting, should have low internalmechanical stress, and should show sufficient ductility to withstandthermal stress. As for the seed layer preferred base layers are made ofnickel or alloys thereof. Examples of other possible metals for the baselayer comprise Pd, Au, Ag, Co and Sn and alloys thereof.

[0069] The contact forming material filling the grooves as embeddedconductors should be a material with a high conductivity. To this endthe preferred material is copper.

[0070] In the present specification the two electroless plating stepshave been described mainly with reference to electroless nickel plating,which is in accordance with the preferred embodiment. However otherelectroless metal plating using a suitable metal having good propertiesas seed layer and as conductive base layer, respectively, may becontemplated as well. In case of such alternative metals the platingconditions including the compositions of the baths should be adapted tothe metal in question. Such adaption is within the abilities of theperson skilled in the art and suitable bath systems are available on themarket. Examples of alternative metals comprise Pd, Au, Ag, Co, Sn andalloys thereof including alloys with Ni.

[0071] In the same way also the electrolytic plating has been describedwith reference to electrolytic copper plating, which presently is thepreferred embodiment. However other electrolytic metal plating using ametal having good electrical conducting properties may be contemplatedas well. In case of such alternative metals the plating conditionsincluding the composition of the bath should be adapted to the metal inquestion. Such adaption including the choice of levelling andsuppressing additives is within the abilities of the person skilled inthe art and suitable bath systems are available on the market. Examplesof alternative metals for the contact forming material comprise Au, Ag,Sn and Ni.

EXAMPLE

[0072] Starting Material

[0073] Use was made of conventional wafers of silicon in the form ofsquares of about 13×13 cm with rounded corners and a thickness of 300 μmdoped p-type. Such wafers are commercially available, for example byBayer Solar GmbH or PV Silicon GmbH.

[0074] P-Doping and SiN_(x) Deposition

[0075] The wafers were etched, textured and cleaned (by subsequentlysubmerging the wafers in a base, water, an acid and water at atemperature of up to 90° C.). Then the front surface, i.e. the lightincident surface, was treated with POCl₃ in a quartz tube furnace atabout 800-900° C. to provide a layer of n-type doped silicon at thefront surface by stacking the wafers in a back-to-back manner.Thereafter silicon nitride was deposited in second quartz tube furnaceat 800-900° C. under low pressure by LPCVD (Low Pressure Chemical VapourDeposition) using dichlorosilane+NH₃-gas to obtain a layer of siliconnitride (SiN_(x)) on the front surface and the edges of the wafers. Thelayer of silicon nitride is electrically insulating, light transparent,not catalytic for electroless plating and acts as an antireflectioncoating for the solar cell.

[0076] The wafers were then coin stacked to protect the surfaces andleave the edges exposed to plasma etch with C₂F₆+oxygen to remove thelayer of silicon nitride and expose the edges.

[0077] The back surface was exposed by plasma etching.

[0078] Laser Grooving

[0079] Thereafter a number of grooves were laser cut in the frontsurface through the layer of silicon nitride making a grid of grooves.Each groove has a transverse cross-section comprising a rectangular parthaving a width of 20 μm and a depth of about 30 μm and a V- or U-shapedcross-section in the bottom giving a total depth of 40 μm. The groovepattern comprises a first group of 80 parallel grooves (1.5 mm pitch)distributed over the front surface and a second group of groovesperpendicular to the first group and joined in two bundles with adistance of about 6 cm from each other. Each bundle comprises 14parallel grooves within a width of about 1.5 to 2 mm.

[0080] The laser cut grooves penetrate through the submicron siliconnitride layer and the n-type silicon, which means that the silicon inthe grooves is largely p-type silicon. To make the n-type silicon thegrooves were first etched by submerging the wafers in a base, water, anacid and water at temperatures up to 50° C. Then the surface in thegrooves was treated with POCl₃ in a quartz tube furnace at about 1000°C. to provide a layer of n-type doped silicon in the grooves.

[0081] Aluminium Deposition

[0082] A deposit of aluminium was provided on the back surface of thewafers by PVD (Physical Vapour Deposition) and the deposit was sinteredin a quartz tube furnace at 700° C.

[0083] Seed Layer

[0084] A seed layer of electroless nickel was plated on the exposedsurfaces in the grooves, on the edges and on the back surface using atype AL100 bath from Enthone™-OMI. This system is a nickel sulphatebased solution having a Ni²⁺ content of 6 g/l and a sodium hypophosphitecontent of 20 g/l and further containing complexing agent and buffer.The pH of this solution was adjusted to 9.7-10 with hydroxide solutionand the plating process was performed at 50-51° C. in 100 seconds. Thethickness of the plated seed layer was about 0.1 μm. Then the seed layerwas sintered to the silicon surface at 400° C. in an inert atmosphere ofnitrogen.

[0085] Electrical Conducting Base Layer

[0086] An electrical conducting base layer of electroless nickel wasplated on the top of the seed layer using an Enplate™ Ni 429 E bath fromEnthone™-OMI. This system is a nickel sulphate based solution having aNi²⁺ content of 6 g/l and a sodium hypophosphite content of 20 g/l andfurther containing complexing agent (20 g/l), stabilisers and buffersand the plating process was performed at 75-78° C., pH 6.0-6.2, in 12minutes. The thickness of the plated base layer was about 2 μm.

[0087] Electrolytic Copper Plating

[0088] Each wafer was fixed on a cathode jig clamping the nickel layerprovided on one of the edges adjacent to the one end of the second groupof grooves, i.e. those forming the two bundles of grooves. Over thenickel layers a copper plating was provided using a UBAC™ ER bath fromEnthone™-OMI with a constant cell voltage of 2.0 volts in about 6minutes. The UBAC™ ER bath solution contains 180-240 μl copper sulphate(CuSO₄.5H₂O), 45-90 g/l sulphuric acid (H₂SO₄), 20-80 mg/l chloride ion(Cl⁻), 1.5-2.5 mil/l UBAC™ ER M Brightener and 0.1-0.5 ml/l UBAC™ ER LBrightener. This system of brighteners comprises an organic sulphurcompound of the type R₁—S—S—R₂ (R₁ and R₂ being alkyl sulphonate groups)which acts as a suppressing additive, a phenazonium dye, which act as alevelling additive, and finally a carrier brightener of the type blockcopolymer of ethylene oxide and propylene oxide having an approximatemolecular weight of 2000.

[0089] By the plating the grooves were completely filled with copper asshown on FIG. 1a and a layer of copper was deposited on the back surfaceand the edges.

[0090]FIG. 1b which is a SEM image of a groove that has been filled by aprocess of the present invention, wherein the process was stopped halfway through, shows, that the filling of the groove essentially proceedsfrom the bottom of said groove. In contrast FIG. 2 which is a SEM imageof a groove that has filled by an electroless process of prior art showsthat the filling of the groove is accompanied by formation of a void inaddition to overplating on the light incident surface.

[0091] Laser Edge Isolation

[0092] The undesired electrically conductive deposits of nickel andcopper on the edges were removed by laser cutting of grooves acting aslines of fracture and subsequent breaking off. In this way theshort-circuit between the embedded copper contacts in the front surfaceand the copper contact on the backside was eliminated. A test of thesolar cell demonstrated an efficiency of 16.5%.

[0093] The obtained wafers can be connected in series to form a solarcell panel.

[0094] The above description of the invention reveals that it is obviousthat it can be varied in many ways. Such variations are not to beconsidered a deviation from the scope of the invention, and all suchmodifications which are obvious to persons skilled in the art are alsoto be considered comprised by the scope of the succeeding claims.

1. A process for the metallising of one or more contacts of a buriedgrid solar cell having a body of doped semiconductor material, whichbody has two major opposing surfaces forming a light incident surfaceand a backside both provided with one or more electrical contacts, andwhich body further has one or more edges between the major opposingsurfaces, wherein the electrical contact or contacts at the lightincident surface is/are formed by conducting material being arranged ina pattern of one or more grooves into the semiconductor material at thelight incident surface, comprising the steps of a) providing thesemiconductor body with a p/n-junction and an electrically insulatinglayer on the light incident surface and optionally on other surfaces,which layer is light transparent and not catalytic for electrolessplating, b) providing an exposed surface on one or more of the edges, c)providing one or more grooves with a depth of 20-50 μm from the lightincident surface through the insulating layer and into the semiconductorbody and a width of 10-30 μm at the level of the light incident surface,d) doping the exposed material in the grooves obtained in step c) toreestablish the p-n-junction in the material below the surface in thegrooves, e) applying a seed layer on the exposed semiconductor materialin the grooves by electroless plating followed by sintering, f) applyingan electrically conducting base layer by electroless plating on top ofthe seed layer obtained in step d), and g) filling the grooves with anelectrically conducting contact forming material by electrolytic platingusing a conventional electrolytic bath further comprising a levellingadditive and a suppressing additive and using substantially constantcell voltage.
 2. A process according to claim 1, wherein the groovesprovided in step (d) includes i) a first group consisting of a number ofessentially parallel grooves distributed mutually spaced over the majorpart of the light incident surface, and ii) a second group of one ormore bundles of narrowly spaced grooves intersecting the first group ofgrooves (i), whereby the material provided in step (e+f+g) forms acorresponding first group of embedded conductors and a correspondingsecond group of embedded conductors, which second group of conductorsforms one or more bundle bus-bars electrically connected to the firstgroup of embedded conductors.
 3. A process according to claim 1 or 2,wherein the exposed surface of semiconductor material in one or more ofthe grooves in at least one end is extended to at least a part of atleast one adjacent exposed edge surface and that the seed layer and theelectrically conducting base layer provided in steps (e) and (f),respectively, are applied on the thus communicating exposed surfacesensuring an electrical contact between the base layer formed in thegrooves and a base layer formed on said part(s) of the edge(s) ensuringa good electrical contact from a clamping jig of an electrolytic platingdevice used in step (g) through the base layers on the edges to the baselayers in the grooves.
 4. A process according to claim 3, using asemiconductor body which has been provided with a coating of aluminiumon the backside in a step preceding step e), wherein the aluminiumcoating optionally is activated by etching of the aluminium oxide layerand wherein steps (e+f+g) further include application of a seed layer, abase layer and a deposit of the contact forming material, respectively,on the aluminium coating, whereby electrically communicating base layerson the grooves and edge(s) and the backside are formed in step (f) andan electrically communicating deposit of the contact forming material inthe grooves, on the edge(s) and on the backside is formed in step (g)and wherein a portion of the electrically conducting layers on theedge(s) formed in steps (e+f+g) are removed to eliminate a short-circuitthrough the electrically conducting layers on the edge(s) between theelectrical contacts on the two major opposing surfaces of thesemiconductor.
 5. A process according to claim 2, wherein the jig isclamped to an electrically conducting layer on one of the edgescommunicating with the second group of one or more grooves and whereinthe semiconductor body is lifted from or lowered into the electrolyticbath during step (g) in such a way that grooves of the first grouplocated at further distance from the electrically conducting layer onsaid edge are submerged for a longer period of time in the bath ascompared to grooves of the first group closer to said edge.
 6. A processaccording to any one of the preceding claims wherein the contact formingmaterial in the grooves essentially fills the grooves withoutoverplating the electrically insulating light transparent layer.
 7. Aprocess according to any one of the preceding claims wherein the body ofsemiconductor material comprises a member of the group consisting ofsilicon, gallium arsenide, indium phosphide, copper indium selenide andzinc oxide.
 8. A process according to any one of the preceding claims,wherein the seed and/or the base layer(s) comprise(s) a member of thegroup consisting of Pd, Au, Ag, Co, Sn and Ni and an alloy thereof.
 9. Aprocess according to any one of the preceding claims, wherein thecontact forming layer(s) comprise(s) Cu.
 10. A buried grid solar cellcomprising a body of doped semiconductor material having two majoropposing surfaces forming a light incident surface and a backside bothprovided with one or more electrical contacts and which body further hasone or more edges between the major opposing surfaces, wherein theelectrical contact or contacts at the light incident surface is/areformed by conducting material being arranged in a pattern of one or moregrooves into the semiconductor material at the light incident surface,which light incident surface is provided with an electrically insulatinglight transparent coating layer interrupted by the grooves, whichgrooves have a depth of 20-50 μm and a width of 10-30 μm at the level ofthe light incident surface, and have a seed layer coating the surfacesin the grooves on the top of which the grooves have an electricallyconducting base layer, on the top of which the grooves further arefilled with an electrically conducting contact forming materialessentially without voids and not overplating the electricallyinsulating light transparent layer.
 11. A solar cell according to claim10, wherein the seed layer and the electrically conducting base layerboth have been provided by electroless plating, and the electricallyconducting contact forming material has been provided by electrolyticplating using substantially constant cell voltage in a conventionalelectrolytic bath further comprising a levelling additive and asuppressing additive.
 12. A solar cell according to claims 10 or 11,wherein the semiconductor material comprises a member of the groupconsisting of silicon, gallium arsenide, indium phosphide, copper indiumselenide and zinc oxide.
 13. A solar cell according to any one of theclaims 10-12, wherein the contact forming material comprises Cu.
 14. Asolar cell according to any one of the claims 10-13, wherein the seedlayer comprises a member of the group consisting of Pd, Au, Ag, Co, Snand Ni and an alloy thereof.
 15. A solar cell according to any one ofthe claims 10-14, wherein the electrically conducting base layercomprises a member of the group consisting of Pd, Au, Ag, Co, Sn and Niand an alloy thereof.
 16. A solar cell according to any one of theclaims 10-15, wherein the body of semiconductor material is a dopedwafer.
 17. A solar cell obtainable by the process as claimed in any oneof the claims 1-9.